1. Field of the Invention
This invention relates to generally to integrated circuit memory devices, and more particularly to improving access cycle time for dynamic random access memories.
2. Related Art
For even inexpensive microprocessors, operating speed has increased dramatically in recent years. Just a few years ago inexpensive desktop computing systems commonly had microprocessors that operated at clock speeds below 500 million cycles per second. Today microprocessors in even relatively inexpensive desktop computing systems commonly operate at speeds of about 1 billion cycles per second. There is also a trend toward higher performance, and hence higher speed, for even less expensive, embedded processors in applications such as personal digital assistants, cell phones, electronic books, watches, etc. This is particularly brought on by the demand for rendering of images by such devices, such as for Internet browsers.
One of the consequences of this trend is a demand for higher speed memory systems. The speed of a dynamic random access memory xe2x80x9c(DRAMxe2x80x9d) is characterized by its random access cycle time, which is largely determined by the time to complete all the random access operations in a cycle, including word line activation, signal development on the bit lines, bit line sensing, signal write back, word line deactivation and bit line precharging. One approach to improving DRAM cycle time is described in the above cross referenced, related application, according to which memory cell contents is not written back each cycle, in order to reduce cycle time.
It is well known to use reference cells in DRAM. See, for example, Cho et al., U.S. Pat. No. 5,140,556, xe2x80x9cSemiconductor Memory Circuit Having Dummy Cells Connected To Twisted Bit Lines;xe2x80x9d Hidaka et al., U.S. Pat. No. 5,461,589, xe2x80x9cBit Line Structure For Semiconductor Memory Device With Bank Separation At Crossover Regions;xe2x80x9d Kinney, U.S. Pat. No. 5,995,408, xe2x80x9cNonvolatile Thorough Electric Memory With Folded Bit Line Architecture;xe2x80x9d and Keeth, U.S. Pat. No. 6,043,562, xe2x80x9cDigit Line Architecture For Dynamic Memoryxe2x80x9d (all discussing performance related layout issues relating to memory cells and associated reference cell""s, also known as xe2x80x9cdummy cellsxe2x80x9d). See also Hideto et al., Japanese Patent 10,255,461, xe2x80x9cSemiconductor memoryxe2x80x9d (discussing a decoder for selecting which dummy word line to associate with which word line); and Akira, Japanese Patent3-276758 (discussing sharing of dummy word lines and ensuring adjacent bits are sensed in different cycles, so that a bit line may be shared between adjacent bit lines and consequently a word line length may be reduced). However, neither the related application, nor any of the other above references disclose changes in operation architecture or sequence to reduce memory system cycle time in connection with memory systems utilizing reference cells. Therefore, a need exists for further improvements.
The foregoing need is addressed in the present invention. In one aspect of the invention, a memory apparatus includes a number of memory cells addressable by word and bit lines. The true bit line in a bit line pair has ones of the memory cells coupled to respective ones of a first set of the word lines and has first and second reference cells coupled to respective first and second odd reference word lines. The complement bit line has ones of the memory cells coupled to respective ones of a second set of the word lines and has first and second reference cells coupled to respective first and second even reference word lines.
Stated generally, it is advantageous to include reference cells in pairs, as in the manner just described, because this enables using one of the reference cells during a read cycle, and precharging (that is, restoring) the other one during the same cycle. Then, in the next cycle, the reference cell that was just precharged can be used, while the reference cell that was just used can be restored. This saves time during each cycle because if there were only one reference cell for a bit line, the cell would have to be used and then restored during the same cycle.
More specifically, the memory apparatus is operable during a voltage development interval of a first read cycle, for a selected one of the word lines and bit line pairs, to conductively couple the corresponding memory cell to one of the bit lines and conductively couple the first one of the reference cells to the other one of the bit lines. The bit line pairs are coupled to respective sense lines of sense amplifiers by isolation circuitry, for selectively isolating the bit lines pair from the respective sense lines and sense amplifiers. During the voltage development interval a voltage differential develops on the selected bit line pair and is transmitted to the corresponding sense line pair. For a reference cell precharging interval that is concurrent with at least a portion of the voltage development interval, the apparatus precharges a second reference cell.
In another aspect, for a voltage detection interval the sense amplifier is enabled for the bit line pair and corresponding sense line pair. For a bit line precharging interval that is concurrent with at least a portion of the voltage detection interval, the corresponding sense line pair is isolated from the selected bit line pair and the selected bit line pair is precharged. The isolating of the sense lines from the bit lines is advantageous because it enables this overlapping of the voltage detection interval with the bit line precharging interval, which also reduces the time required for the read cycle.
The sense amplifier for the corresponding sense line pair is operable during the first read cycle voltage detection interval to detect the voltage differential developed on the sense lines. The detected voltage is transmitted to a static memory during the voltage detection interval. By saving the detected voltage to static memory the contents of the dynamic memory cell can be read in a xe2x80x9cdestructive xe2x80x9d manner. This is advantageous because it enables the precharging (also referred to as xe2x80x9crestoringxe2x80x9d) of the bit lines without regard for what voltage was asserted on them by the dynamic memory cell, making the bit line precharging faster.
The isolating of the sense lines from the bit lines is also advantageous because it permits precharging the sense lines during a sense line precharge interval (during which the sense amplifier is, of course, disabled) that is much shorter than the time interval required to precharge the bit lines, since the sense lines are relatively much shorter in length. That is, it permits the bit line precharging interval to begin earlier and then overlap in time with a portion of the sense line precharge interval.
Other advantages and objects of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.